In the manufacture of microelectronics, circuits and other logic must be placed on chips and routed under certain wireability and timing constraints. Specifically, the electric circuits must be placed and routed in such a way that all wiring corresponding to the nets joining the electric circuits can be placed and connected as required. As a rule, routing begins after a floorplan has been laid out and the electric circuits have been placed on the chip. Routing is generally split into a global routing step followed by a detailed routing step. During global routing, a complete set of instructions is provided according to which the detailed router is to place actual wiring of every net. The objectives of global routing include a minimization of total interconnect length, a maximization of the probability that the detailed router can complete the routing, and a minimization of critical path delay. Thus, the global routing step determines the channels to be used for each interconnect. Using this information, the detailed router determines the exact location and layers for each interconnect. Depending on the quality of placement and of global routing as well as on local wiring requirements, detailed routing often produces local areas with inferior quality of wiring which unnecessarily crowds the wiring channels and has a negative effect on the design's performance. Such inferior wiring quality includes unconnects (i.e. nets which could not be connected by wiring) as well as so-called scenic routes (i.e. nets which, instead of following minimizing wiring length with long straight segments and few changes of wire level, are composed of many small segments and contain many vias). This kind of inferior quality wiring usually only occurs in relatively small congested areas. In addition to diminishing the design's performance, unconnects and scenic routes squander routing resources, contribute to wiring congestion and can cause “hot spots” on the chip which can lead to overload and failure thereof. The situation is aggravated in the presence of multi-segment nets which underlie a strong requirement to use redundant vias, thus causing additional blockade and making the congestions even worse.
In the past, local wiring improvement was mostly performed manually, requiring a considerable amount of time-consuming interaction by the designer. As an example, FIG. 1 depicts a method flow diagram illustrating conventional wiring improvement: After global and detailed routing 252, 254 of electric circuits in a given placement of cells, an analysis 256 of the routed design was carried out to determine whether critical parameters of the design (such as timing, connection quality etc.) met specifications. If critical parameters were not satisfactory, manual steps 258 were performed, trying to locally “repair” deficient routing results. In the case of unconnects, manual interaction or retries were necessary, because otherwise the local router was unable to finish all routes. If slew and slack timing requirements were not met (due to scenic routes, bad wiring levels etc.), certain nets had to be manually rerouted (step 260), e.g. by straightening nets. All such manipulations were carried out on a trial-and-error basis, making them highly time-consuming and tending to result in unacceptable delays in chip development. Even though some routers comprise “clean steps” features, these were found to often leave the wiring in a worse state than before.
In view of the foregoing, there is a need for an improved method and a system for routing connections between electric circuits on a chip in such a way as enhance wiring resources in congested areas while at the same time limiting wiring congestion.